Discrete Math Quiz: Logic Gates And Circuit Simplification
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Logic Gates And Circuit SimplificationQuestion 1 of 4

A multiplexer circuit has the truth table behavior where output Y equals input D₀ when select lines S₁S₀ = 00, equals D₁ when S₁S₀ = 01, equals D₂ when S₁S₀ = 10, and equals D₃ when S₁S₀ = 11. What Boolean expression represents this multiplexer function?

Y=S1‾S0‾D0+S1‾S0D1+S1S0‾D2+S1S0D3Y = \overline{S_1}\overline{S_0}D_0 + \overline{S_1}S_0D_1 + S_1\overline{S_0}D_2 + S_1S_0D_3
Y=S1S0D0+S1S0‾D1+S1‾S0D2+S1‾S0‾D3Y = S_1S_0D_0 + S_1\overline{S_0}D_1 + \overline{S_1}S_0D_2 + \overline{S_1}\overline{S_0}D_3
Y=(S1‾+S0‾)D0+(S1‾+S0)D1+(S1+S0‾)D2+(S1+S0)D3Y = (\overline{S_1} + \overline{S_0})D_0 + (\overline{S_1} + S_0)D_1 + (S_1 + \overline{S_0})D_2 + (S_1 + S_0)D_3
Y=S1S0‾D0+S1‾S0D1+S1S0‾D2+S1S0D3Y = \overline{S_1S_0}D_0 + \overline{S_1}S_0D_1 + S_1\overline{S_0}D_2 + S_1S_0D_3
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Discrete Math Quiz

Discrete Math Quiz: Logic Gates And Circuit Simplification

Practice Logic Gates And Circuit Simplification in Discrete Math with focused quiz questions that help you check what you know, review explanations, and build confidence with test-style prompts.

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Question 1

A multiplexer circuit has the truth table behavior where output Y equals input D₀ when select lines S₁S₀ = 00, equals D₁ when S₁S₀ = 01, equals D₂ when S₁S₀ = 10, and equals D₃ when S₁S₀ = 11. What Boolean expression represents this multiplexer function?

  1. Y=S1‾S0‾D0+S1‾S0D1+S1S0‾D2+S1S0D3Y = \overline{S_1}\overline{S_0}D_0 + \overline{S_1}S_0D_1 + S_1\overline{S_0}D_2 + S_1S_0D_3 (correct answer)
  2. Y=S1S0D0+S1S0‾D1+S1‾S0D2+S1‾S0‾D3Y = S_1S_0D_0 + S_1\overline{S_0}D_1 + \overline{S_1}S_0D_2 + \overline{S_1}\overline{S_0}D_3
  3. Y=(S1‾+S0‾)D0+(S1‾+S0)D1+(S1+S0‾)D2+(S1+S0)D3Y = (\overline{S_1} + \overline{S_0})D_0 + (\overline{S_1} + S_0)D_1 + (S_1 + \overline{S_0})D_2 + (S_1 + S_0)D_3
  4. Y=S1S0‾D0+S1‾S0D1+S1S0‾D2+S1S0D3Y = \overline{S_1S_0}D_0 + \overline{S_1}S_0D_1 + S_1\overline{S_0}D_2 + S_1S_0D_3
Explanation: A multiplexer selects one input based on select lines. Each data input is gated by the AND of the select lines in the appropriate combination: D₀ is selected when both S₁ and S₀ are 0 (S̄₁S̄₀), D₁ when S₁=0 and S₀=1 (S̄₁S₀), etc. Choice B reverses the select conditions, C uses OR instead of AND, and D incorrectly applies De Morgan's law to S₁S₀.

Question 2

Two equivalent circuits implement the same Boolean function. Circuit A uses 8 two-input NAND gates, while Circuit B uses 3 two-input NOR gates and 2 inverters. Assuming identical propagation delays for all gate types, which statement about power consumption is most accurate?

  1. Circuit A consumes more power due to the higher total gate count and switching frequency
  2. Circuit B consumes more power because NOR gates typically have higher power dissipation than NAND gates
  3. Both circuits consume equal power since they implement identical Boolean functions with equivalent outputs
  4. Power consumption depends on input patterns and cannot be determined from gate counts alone (correct answer)
Explanation: Power consumption in CMOS logic depends heavily on switching activity, input transition frequencies, and the specific input patterns applied to the gates. Gate count alone is insufficient to determine power consumption. While Circuit A has more gates, the actual power depends on how often each gate switches, which varies with input patterns. Choices A, B, and C make assumptions about power based solely on gate types or counts.

Question 3

A circuit designer claims that the circuit implementing f(x,y,z)=xyz+xy‾z+x‾yz+x‾y‾zf(x,y,z) = xyz + x\overline{y}z + \overline{x}yz + \overline{x}\overline{y}z can be simplified to just a single gate. Which single gate type correctly implements this function?

  1. A direct connection to input z, since the function reduces to z regardless of x and y values
  2. A single OR gate with inputs x and z, since the function simplifies to x + z after factoring
  3. A buffer gate with input z, as all terms contain z and the remaining expression equals 1 (correct answer)
  4. A single XOR gate with inputs x and y, since the function depends only on the relationship between x and y
Explanation: Factoring out z: f(x,y,z) = z(xy + xȳ + x̄y + x̄ȳ). The expression in parentheses covers all possible combinations of x and y (00, 01, 10, 11), so it equals 1 for all inputs. Therefore f = z·1 = z. A buffer gate simply passes its input unchanged. Choice A describes a wire connection rather than a gate, B gives wrong simplification, D ignores the z dependency.

Question 4

A logic circuit implements the function f(x,y,z)=xy+x‾z+yzf(x,y,z) = xy + \overline{x}z + yz. After applying Boolean algebra simplification, which expression represents the most reduced form?

  1. xy+x‾zxy + \overline{x}z, since the consensus term yz is redundant by the consensus theorem (correct answer)
  2. xy+z(x‾+y)xy + z(\overline{x} + y), by factoring common terms without eliminating any minterms
  3. x(y+z)+x‾zx(y + z) + \overline{x}z, by distributing x across the first two terms
  4. y+x‾zy + \overline{x}z, since xy is absorbed by the combination of other terms
Explanation: The consensus theorem states that AB + ĀC + BC = AB + ĀC, where the term BC is redundant. Here, xy corresponds to AB, x̄z corresponds to ĀC, and yz corresponds to BC. Therefore, yz can be eliminated, giving xy + x̄z. Choice B is factored but not minimal, C is incorrectly distributed, and D incorrectly eliminates xy.